'Vhdl for Synthesis\r'

'ELE591 †VHDL for Synthesis Issue 1. 0: 1st December 2010 The purpose of this testing groundoratory audition is to familiarise you with the principles of VHDL for synthesis targeted at programmable logical system finesses. You give observe how various VHDL descriptions result in establish Transfer Level (RTL) implementations and how these can be utilise within specific logic devices. The principles of back-annotation will withal be explored and how this can be used to learn performance limitations of specific hardw are imagery mappings.\r\nThis lab assumes you are already familiar with Xilinx ISE and ModelSim, given that ELE335 is a prerequisite for this staff. If necessary, consult the ELE335 lab guide, which is included in the Coursework section of the ELE591 module webpage. Most of the VHDL archives needed for this lab are also available from the same location. engagement 1: fill: To compare the results of different architectural descriptions for the same entity step: • shape a undertaking named â€Å"exercise1”. minimal brain dysfunction the send ex1a. vhd as a â€Å"VHDL module” • Select the Spartan3 as the target device hive up and synthesize the VHDL description and encounter the externalize history wedge, paying particular attention to the resource practice session summary (and clock path analysis). Also examine the RTL protrude. • Repeat with the files ex1b. vhd and ex1c. vhd and compare the results. illustration 2: Aim: To beautify the use of â€Å"don’t trade” values in synthesis steps: • Create a date named â€Å"exercise2”. Add the file docare. vhd as a â€Å"VHDL module” • compile and combine the picture targeting the Spartan3 device • Add the file dontcare. hd as a â€Å"VHDL module” and repeat the synthesis. • Compare the insure files. usage 3: Aim: To illustrate logic resource requirements for conditional versus mutually exclusive input conditions Steps: • Create a project named â€Å"exercise3”. Add the file cond. vhd as a â€Å"VHDL module” • Compile and synthesise the design targeting the Spartan3 device • Add the file exclusiv. vhd as a â€Å"VHDL module” and repeat the synthesis. • Compare the calculate files. Also compare the times at the design logic level and at the place and route level. performance 4:\r\nAim: To review resource and timing requirements of a analyzable readjust function Steps: • Create a project named â€Å"exercise4”. Add the file cntpt. vhd as a â€Å"VHDL module” • Compile, synthesise and affect the design targeting the Spartan3 device • Review the report file paying particular attention to the reset equation. • at a time examine the file cntpt2. vhd which employs a synchronous complex reset. • Attempt to simulate the designs and comment on the reset timing in twain ca ses. Exercise 5: Aim: To compare CPLD and FPGA implementations of a FIFO design Steps: Create a project named â€Å"exercise5”. Add the file fifo. vhd as a â€Å"VHDL module” • Compile and synthesise the design targeting the Spartan3 device • Recompile the design for a Coolrunner2. • Compare the report files and the resulting RTL layouts. • Place and route both designs • Compare the design files paying particular attention to the supreme operational frequency and the amount of resources used. Which timing parameter is the limiting factor on the direct frequency in each case? Exercise 6: Aim: To illustrate the effects of unstated memory\r\nSteps: • Create a project named â€Å"exercise6”. Add the file memcont. vhd as a â€Å"VHDL module” • Compile and synthesise the design targeting the Spartan3 device. • Examine the report file. • Add the file memcont2. vhd as a â€Å"VHDL module”. In this f ile the signal assignments for oe, we and addr are outside from under the reset condition. • Compile and synthesise the design targeting the Spartan3 device. • Compare the report file with that of the original design. drift that implicit memory resulted in the creation of a combinatorial latch.\r\nExercise 7: Aim: To illustrate the advantage of â€Å"one hot” encoding of spectacular state-machines implemented in FPGA architectures Steps: • Create a project named â€Å"exercise7”. Add the file onehot. vhd as a â€Å"VHDL module” • Compile and synthesise the design targeting the Spartan3 device • Place and route the design and al-Quran the subjugate of logic cells required, the setup time, clock-to-output delay and maximum operating frequency. • Now employ the file notonehot. vhd. This uses the synthesis light beam to assign values to the various enumerated states. Compile and synthesise the updated design targeting the Sp artan3 device. • Place and route the design and record the number of logic cells required, the setup time, clock-to-output delay and maximum operating frequency. • Compare the results with the original design. This series of experiments should be written up as an INDIVIDUAL testis lab report. The report will be contain to a maximum of 8 pages of main textbook (i. e. omitting title page etc). The hand-in date is the 17th December, unless you are informed otherwise.\r\n'